Pritha Banerjee

Employment

• University of Calcutta Dr.
  2009 - Present

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (15)

• Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction
  Integration 2023 DOI: 10.1016/j.vlsi.2023.04.007
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• Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography
  2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC) 2022 DOI: 10.1109/vlsi-soc54400.2022.9939588
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• Stitch-avoiding Global Routing for Multiple E-Beam Lithography
  2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID) 2022 DOI: 10.1109/vlsid2022.2022.00037
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• A study on flare minimisation in EUV lithography by post‐layout re‐allocation of wire segments
  IET Circuits, Devices & Systems 2021 DOI: 10.1049/cds2.12028
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• Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification
  2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2019 DOI: 10.1109/isvlsi.2019.00047
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• Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography
  2017 IEEE International Conference on Computer Design (ICCD) 2017 DOI: 10.1109/iccd.2017.71
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• Flare reduction in EUV Lithography by perturbation of wire segments
  2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2015 DOI: 10.1109/vlsi-soc.2015.7314383
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• An efficient and effective analytical placer for FPGAs
  Proceedings of the 50th Annual Design Automation Conference 2013 DOI: 10.1145/2463209.2488746
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• Cone-based placement for field programmable gate arrays
  IET Computers & Digital Techniques 2011 DOI: 10.1049/iet-cdt.2009.0058
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• FPGA placement using space-filling curves
  ACM Transactions on Embedded Computing Systems 2009 DOI: 10.1145/1596543.1596546
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