Suyash Kushwaha

About

I recently graduated with PhD degree in Microelectronics & VLSI Design from IIT Ropar, Punjab, India. My work is around modeling and design optimization of emerging copper graphene hybrid interconnects for advamced packaging. I have capabilities of simulation/modeling interconnects at advance technology nodes with EM solvers, circuit simulators via machine learning.

Employment

Employment history is unavailable.

Education

• Indian Institute of Technology Ropar PhD
  2020 - 2026
• Indian Institute of Technology Roorkee M.Tech
• Dr. A.P.J. Abdul Kalam Technical University B.Tech

Projects & Funding

Projects & funding information is unavailable.

Publications (15)

• Machine Learning-Based Performance Optimization of Copper–Graphene Heterointerconnects
  IEEE Transactions on Components, Packaging and Manufacturing Technology 2026 DOI: 10.1109/TCPMT.2026.3658703
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• Impact of Scaling on Large Crossbar Arrays for Neuromorphic Applications
  2025 IEEE 29th Workshop on Signal and Power Integrity (SPI) 2025 DOI: 10.1109/spi64682.2025.11014309
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• Performance Enhanced Copper-Graphene Hetero Interconnect Structures in Crossbar Arrays for Neuromorphic Computing
  IEEE Journal on Multiscale and Multiphysics Computational Techniques 2025 DOI: 10.1109/JMMCT.2025.3593872
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• Signal Integrity Analysis of Ultra-scaled Copper-Graphene Heterogeneous Interconnect Structure
  2024 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) 2024 DOI: 10.1109/edaps64431.2024.10988469
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• Design and Analysis of 3D Integrated Folded Ferro-Capacitive Crossbar Array (FC²A) for Brain-Inspired Computing System
  IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2024 DOI: 10.1109/JETCAS.2024.3432458
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• Modeling and Comparing the Impact of Resistive and Capacitive Crossbar Associated Parasitics of Neuromorphic Circuits
  2024 31st International Conference on Mixed Design of Integrated Circuits and System (MIXDES) 2024 DOI: 10.23919/mixdes62605.2024.10614061
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• Space Mapped Neuromodeling for Fast & Accurate Signal Integrity Analysis of Rough On-chip Copper Interconnects
  2023 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) 2023 DOI: 10.1109/edaps58880.2023.10468464
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• An Efficient Electrical-Thermal Co-Design Methodology for Analysis of High-Speed PCB Interconnects
  2023 IEEE MTT-S International Conference on Numerical Electromagnetic and Multiphysics Modeling and Optimization (NEMO) 2023 DOI: 10.1109/nemo56117.2023.10202286
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• Modeling and Analysis of CMOS-based Folded Memristive Crossbar Array for 3D Neuromorphic Integrated Circuits
  2023 IEEE 73rd Electronic Components and Technology Conference (ECTC) 2023 DOI: 10.1109/ectc51909.2023.00164
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• Fast Multi-ANN Composite Models for Repeater Optimization in Presence of Parametric Uncertainty for on-Chip Hybrid Copper-Graphene Interconnects
  IEEE Access 2023 DOI: 10.1109/ACCESS.2023.3335306
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