0009-0009-5619-4282 Employment
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Publications (8)
- An Enhanced Bulk-Driven Double Tail Dynamic Comparator with Fast Discharge for Improved Speed and Energy Efficiency Save
- Comprehensive analysis of tree-shaped nanosheet FETs in junctionless, accumulation, and inversion structures at sub-5 nm node for next-generation digital, analog/RF and circuit applications Save
- Design optimization of spacer engineered junctionless-fishbone (JL-FB) FET at 5 nm technology node: device to circuit level implementation Save
- First demonstration of leaky-integrate and fire neuron based GAA nanosheet FET with ultra-low energy consumption down to 0.8fJ/spike for spiking neural network applications Save
- Physical insights into optimization of dual metal gate junctionless tree-shaped FETs at sub-5 nm technology node: device to circuit approach Save
- Interface trap dynamics and thermal effects in novel junctionless dual gate inverted-U-shaped FinFETs for sub-5 nm node: device to circuit level implementation Save
- Design and analysis of circular sheet junctionless double gate vertical nanotube (CSJL-DG-VNT) FET for DC/Analog/RF applications: device to circuit implementation Save
- Design optimization of junctionless bottom spacer tapered FinFET: Device to circuit level implementation Save