0000-0001-7924-8575 About
Aruru Sai Kumar received B.Tech in Electronics and Communications Engineering in 2008 from JNTU Hyderabad, India and M.Tech in VLSI Design in 2010 from VIT University, Vellore, India. His higher education includes full-time Ph.D. in VLSI Design
at National Institute of Technology, Warangal, which was completed in the year 2022. He is currently working as Assistant Professor Senior Grade 2 in VIT-AP University, Amaravati, AP, India. His research interests focus on Network-on-Chip architecture design, application mapping in 2-D and 3-D environments, Low-Power VLSI Design and Nanoscale Device Modelling i.e. FinFET, Nanowire FET and Nanosheet FET devices.
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Publications (77)
- Optimized reversible QCA full adder subtractor for low latency and energy efficiency Save
- Hybrid Simulation and Formal Verification of a Power-Gated RV32I Pipeline with State Retention Save
- Analysis of multi-bridge-channel FET for CMOS logic applications Save
- Analyzing Fully Depleted SOI NC‐MOSFET for Enhanced Bio‐Sensor and Digital Circuit Applications Save
- A novel design of high-speed write assist design for single-stacked 9T-ST SRAM Save
- Gate Stack Analysis of Junctionless Multi-Bridge-Channel FETs for Sub-3 nm Chips Save
- Multi-bit error detection and correction codes implementation using generator-parity check matrices technique Save
- Principle Study of Nanosheet Field-Effect Transistors with Transition Metal Dichalcogenide Channel Materials Save
- Quantum Transport Analysis of Nanosheet FETs Utilizing 2D Semiconductor Materials Save
- Unveiling House Price with Machine Learning Algorithm Save
- A Comparator Tree Design with Optimized Quantum Cost Using Reversible Logic Techniques Save
- A Novel ASK Reversible Gate and its Implementation in Ripple Carry Adder Design Save
- A Novel Approach to Implement a 4-Bit Vedic Multiplier Using Reversible Techniques Save
- A Novel Design of Area Efficient Full Adder Architecture Using Reversible Logic Gates Save
- A Novel Design of High Performance Two-Stage Operational Amplifier using CMOS Technology Save
- A Novel Reversible Gate Design for Comprehensive Logic and Arithmetic Operations Save
- A novel design of collapsed supply and boosted bit-line swing write driver for fast write access 9T SRAM Save
- A novel energy efficient 4-bit vedic multiplier using modified GDI approach at 32 nm technology Save
- An Efficient 8-Bit Adder/Subtractor Design Utilizing Reversible Logic Techniques Save
- An Efficient BCD Adder Design Utilizing Reversible Logic Techniques Save