RA
ramesh kumar aytha
VNR Vignana Jyothi College of Engineering and Technology, Osmania University, Bharath University
Research areas: Engineering · Electrical and Electronic Engineering · Embedded Systems and FPGA Applications · Embedded Systems Design Techniques · Digital Filter Design and Implementation
0000-0001-9316-3404
Employment
-
VNR Vignana Jyothi College of Engineering and Technology ASSOCIATE PROFESSOR
Education
- 2011 - 2023
Projects & Funding
Projects & funding information is unavailable.
Publications (20)
- A precision 0.72 V sub-bandgap reference with 5.02 ppm/°C TC and optimized line and PSR characteristics Save
- Analytical Modelling of RF MEMS Series Switch for Low Pull-in Voltage and Better RF Performances Save
- Implementation of Band Pass Filter Using CSRR and SRR Structures for Millimeter Applications Save
- FPGA Implementation of Transposed FIR Filter for De-Noising ECG Signals Save
- FPGA Implementation of Turbo Encoder for Digital Communication Systems Save
- FPGA-based serial communication with enhanced data flow control using FIFOs and UART interface Save
- Implementation of 5G NR Primary and Secondary Synchronization in FPGA Save
- Implementation of 5G New Radio Secondary Synchronization on FPGA Save
- Machine learning for IoT-based smart farming Save
- Design and Implementation of Optimized FIR Filter using CSA and Booth Multiplier for High Speed Signal Processing Save
- FPGA Implementation of ECG Denoising using Kaiser Window Technique Save
- FPGA Implementation of Systolic FIR Filter Using Single-Channel Method Save
- High performance FIR Architecture for EOG Signal Noise Supression Save
- Realization of 5G NR Primary Synchronization Signal Detector Using Systolic FIR Filter Save
- FPGA Implementation of 5G NR Primary and Secondary Synchronization Save
- FPGA Implementation of High Performance Hybrid Encryption Standard Save
- Implementation of 5G NR Primary and Secondary Synchronization Save
- Energy Efficient Adiabatic Logic Against Power Analysis Attacks for IOT Applications Save
- The fastest possible solution to the weighted water-filling problems Save
- FPGA implementation of secondary synchronization channel detector for WCDMA systems Save