Pooja Joshi

Employment

Employment history is unavailable.

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (9)

• LUT-Based Mapping of Logic Functions to Partitioned Memristive Crossbar Using MAGIC for High-Throughput Computing
  Pooja K. Joshi, Anindita Chakraborty, Hafizur Rahaman
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2026 DOI: 10.1109/TCAD.2025.3581866
  +Save
• A comprehensive review on ReRAM-based accelerators for deep learning
  2023 International Symposium on Devices, Circuits and Systems (ISDCS) 2023 DOI: 10.1109/isdcs58735.2023.10153519
  +Save
• Memristor based In-Memory Computing for Edge AI Applications
  2023 International Symposium on Devices, Circuits and Systems (ISDCS) 2023 DOI: 10.1109/isdcs58735.2023.10153553
  +Save
• Complementary Memresistive Switch Based Realization of Delay and Toggle Flip-Flop
  2021 Devices for Integrated Circuit (DevIC) 2021 DOI: 10.1109/devic50843.2021.9455941
  +Save
• Low power shorted gate fin-FET based high performance amplifier
  2018 IEEE 8th Annual Computing and Communication Workshop and Conference (CCWC) 2018 DOI: 10.1109/ccwc.2018.8301778
  +Save
• Performance optimization in flip flop circuit design
  2018 IEEE 8th Annual Computing and Communication Workshop and Conference (CCWC) 2018 DOI: 10.1109/ccwc.2018.8301779
  +Save
• Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL
  Pooja K. Joshi, Saurabh Khandelwal, Shyam Akashe
  Journal of Low Power Electronics 2015 DOI: 10.1166/jolpe.2015.1401
  +Save
• Comparative Analysis of MTCMOS and SVL Based Flip Flop Design.
  Journal of Active & Passive Electronic Devices 2015
  +Save
• Implementation of Low Power Flip Flop Design in Nanometer Regime
  Pooja K. Joshi, Saurabh Khandelwal, Shyam Akashe
  2015 Fifth International Conference on Advanced Computing & Communication Technologies 2015 DOI: 10.1109/acct.2015.84
  +Save