0000-0002-0284-7884 About
I am a senior researcher in multi-disciplinary domains of Artificial Intelligence - Machine Learning, Semiconductors, Electronics, Information and Communication Technology with an overall experience of 10+ years (including my doctoral education). I have industry experience of 6+ years in the fields of technology and management besides experience in the academic research labs - MINRO at IIITB, LTRC at IIITH and MST at UniMAP. I have multiple indexed publications (Book Chapters/Journals/International Conferences) in the afore mentioned research domains with main focus on Autonomous Control, Computer Vision, Edge Computing, FPGA, Embedded Systems, Hardware Accelerators, Co-Processors etc. I have been active in R & D consulting with both academia and industry besides being a Technical Program Committee (TPC) member and reviewer with few international conferences and journals. I have received merit-based fellowships/scholarships through-out my education/career and look forward to give back to the society in terms of product innovation and technical contribution. I am member of IEEE (USA), IEICE (Japan) and RISC-V (USA). I have also delivered several talks at various national/international platforms on emerging topics of AI-ML, Hardware design and FPGA based hardware architectures.
Abridged version of my skillset and expertise include:
* Hardware Embedded Boards: AMD-Xilinx ZCU104 (FPGA), Avnet Ultra 96v2 (FPGA), Coral – Google Edge TPU
* EDA/Software: AMD-Xilinx: Vivado HLS, Vivado, SDK, PYNQ; Cadence: Genus, Virtuoso; Siemens (Mentor Graphics) – Semi and Full Custom; MATLAB
* Languages (Digital Design/Programming): Verilog, C/C++, Embedded C, Python
* Hardware Verification: System Verilog, UVM
* Testing: Design for Testability and Built-in Self-Test
* Hardware Interfaces: AMBA-AXI, UART, SPI
* Areas of Interest: AI-ML, FPGA, Edge Computing, VLSI/Embedded System Design, Hardware
Accelerators, Co-Processors, Micro Architecture, Autonomous Control, Computer Vision
Awards/Fellowships/Workshops (only selected):
- DAC Young Fellow – 58th Design Automation Conference, San Francisco, USA
- Google Research - Asia Pacific Research Symposium
- IEEE- ITC and VLSID – Full Conference Fellowships
- Cadence (High Level Synthesis) - DAC Summer School
- Global Semiconductor Innovation – Chinese American Semiconductor Professional Association
- Telluride Neuromorphic Cognition Engineering
- Common Hardware for Interfaces, Processors and Systems Alliance
***Please feel free to reach out to me for research collaboration and R&D consulting:
[email protected]
Employment
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International Institute of Information Technology
Education
Education history is unavailable.
Projects & Funding
Projects & funding information is unavailable.
Publications (13)
- Fully convolutional network for edge devices—FPGA implementation and analysis for agriculture technology Save
- Heterogeneous Computing of Multi-Agent Deep Reinforcement Learning on Edge Devices for Internet of Things Save
- FPGA implementation of Proximal Policy Optimization algorithm for Edge devices with application to Agriculture Technology Save
- Hardware realization of reinforcement learning algorithms for edge devices Save
- Resource Constrained Hardware Architecture for Training Deep Neural Networks at the Edge - FPGA Implementation Save
- Hardware Realization of Reinforcement Learning Algorithms for Edge Devices Save
- Accelerating the Activation Function Selection for Hybrid Deep Neural Networks – FPGA Implementation Save
- Cellular automata and arbiter PUF-based security architecture for system-on-chip designs Save
- Cellular automata logic block observer based testing for network-on-chip architecture Save
- Test scheduling with built in logic block observer for NoC architecture Save