Zeeshan Ali

About

Zeeshan Ali received the B.Tech. Degree in electronics and communication engineering from Jamia Millia Islamia, New Delhi, India, in 2011, and M.Tech. Degree in electrical engineering from IIT Delhi, New Delhi, in 2017. He obtained his PhD degree at the Department of Electrical Engineering, IIT Bombay, Mumbai, India, in 2023. His research interests include analog/digital frequency synthesizers and mixed-signal circuit design. He began working as a Research Associate since Feb' 23 at the University of Glasgow. He is designing RF/mixed-signal Cryo-CMOS circuits for quantum computing.

Employment

• University of Glasgow Research Associate
  2023 - Present

Education

• Jamia Millia Islamia B. Tech.
  2007 - 2011

Projects & Funding

Projects & funding information is unavailable.

Publications (7)

• De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2025 DOI: 10.1109/TVLSI.2024.3513478
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• Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature]
  Zeeshan Ali, Pallavi Paliwal, Meraj Ahmad +2 more
  IEEE Circuits and Systems Magazine 2024 DOI: 10.1109/MCAS.2024.3383809
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• Impact of Receiver Thermal Noise and PLL RMS Jitter in Radar Measurements
  Zeeshan Ali, Mostafa Elsayed, Girish Tiwari +4 more
  IEEE Transactions on Instrumentation and Measurement 2024 DOI: 10.1109/TIM.2024.3370745
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• Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs)
  Zeeshan Ali, Pallavi Paliwal, Phani Raj +3 more
  IEEE Control Systems Letters 2023 DOI: 10.1109/lcsys.2023.3242830
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• A Fast Locking Ring Oscillator Based Fractional-N DPLL With an Assistance From a LUT-Based FSM
  2022 IEEE International Symposium on Circuits and Systems (ISCAS) 2022 DOI: 10.1109/iscas48785.2022.9937479
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• A Low Jitter Double-Tailed Strong-Arm Latch Based Digital-to-Time Converter (DTC)
  2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2020 DOI: 10.1109/icecs49266.2020.9294801
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• A Fast Settling Fractional-$N$ DPLL With Loop-Order Switching
  Pallavi Paliwal, Vivek H Yadav, Zeeshan Ali +1 more
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2020 DOI: 10.1109/tvlsi.2019.2956100
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