Dr. Sumit kale

Employment

• Delhi Technological University Assistant Professor
  2020 - Present

Education

• Indian Institute of Information Technology Design and Manufacturing Jabalpur PhD
  2012 - 2017
• Shri Govindram Seksaria Institute of Technology and Science M. Tech
  2007 - 2009
• Samrat Ashok Technological Institute B.E.
  2002 - 2006

Projects & Funding

Projects & funding information is unavailable.

Publications (10)

• A Comparative Study of Short Gate and Full Gate Dielectric Modulated Schottky Barrier TFET for Biosensing Application
  Silicon 2022 DOI: 10.1007/s12633-022-01924-z
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• Dielectric Engineered Schottky Barrier MOSFET for Biosensor Applications: Proposal and Investigation
  Silicon 2022 DOI: 10.1007/s12633-021-01191-4
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• Ferroelectric Schottky barrier tunnel FET with gate-drain underlap: Proposal and investigation
  Superlattices and Microstructures 2016 DOI: 10.1016/j.spmi.2015.11.019
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• Impact of underlap channel on analog/RF performance of dopant segregated schottky barrier MOSFET on ultra thin body SOI
  1st International Conference on Emerging Trends in Engineering, Technology and Science, ICETETS 2016 - Proceedings 2016 DOI: 10.1109/ICETETS.2016.7603033
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• Influence of underlap gate length on analog/RF performance of pocket doped Schottky Barrier MOSFET
  2nd International Conference on Electronics and Communication Systems (ICECS), 2015 2015 DOI: 10.1109/ECS.2015.7124764
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• Performance study of high-k gate & spacer dielectric Dopant Segregated Schottky Barrier SOI MOSFET
  2015 2nd International Conference on Electronics and Communication Systems (ICECS) 2015 DOI: 10.1109/ecs.2015.7124762
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• Ambipolar leakage suppression in Ge n-channel Schottky barrier MOSFET
  IETE Journal of Research 2015 DOI: 10.1080/03772063.2015.1021387
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• Design and investigation of double gate Schottky barrier MOSFET using gate engineering
  Micro and Nano Letters 2015 DOI: 10.1049/mnl.2015.0046
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• Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering
  Electronics Letters 2015 DOI: 10.1049/el.2015.0283
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• Impact of Underlap Channel and Body Thickness on the Performance of DG-MOSFET with Si<inf>3</inf>N<inf>4</inf> spacer
  2014 IEEE International Conference on Electron Devices and Solid-State Circuits 2014 DOI: 10.1109/edssc.2014.7061237
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