Ranjan Barik

About

Ranjan kumar Barik received B.Tech degree in Electronics and Communication Engineering from the Biju Patnaik University of Technology in 2011. He joined the Department of Electronics and Telecommunication Engineering, VSS University in 2012 where he is presently carrying out Ph.D research work. His research interests include computer arithmetic, computer architecture, and VLSI design.

Employment

• Perfect vips Techno Solution Design Verification Engineer
  2018 - Present

Education

• VSS University of Technology Ph.D.
  2014 - 2018

Projects & Funding

Projects & funding information is unavailable.

Publications (4)

• An efficient redundant binary adder with revised computational rules
  Computers & Electrical Engineering 2018 DOI: 10.1016/j.compeleceng.2018.09.016
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• Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation
  Journal of Circuits, Systems and Computers 2017 DOI: 10.1142/s0218126617501353
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• Time efficient signed Vedic multiplier using redundant binary representation
  The Journal of Engineering 2017 DOI: 10.1049/joe.2016.0376
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• Efficient ASIC and FPGA implementation of cube architecture
  IET Computers & Digital Techniques 2017 DOI: 10.1049/iet-cdt.2016.0043
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